The constant scaling of the geometry and the supply voltage used in integrated circuits (IC) is pushing the existing metal-oxide-semiconductor field effect transistor (MOSFET) technology to its limits, especially in terms of the switching slope (SS), which is defined as the derivative of log ID with respect to the gate voltage VGS[1]:
      S    ⁢                  ⁢    S    =                    ∂                  V          G                                      ∂                      ψ            S                                    ︸          m                      ⁢                  ∂                  ψ          S                                      ∂                      (                                          log                10                            ⁢                              I                D                                      )                                    ︸          n                    where m is the transistor body factor which depends on the electrostatic control of the channel and n depicts the change in the drain current with respect to changes in the surface potential. It is well known that MOSFETs or any other semiconductor device that relies on thermionic emission of charge carriers is ultimately limited by an SS of 60 mV/dec at room temperature due to the uncompressible limitation of the n factor equation above [2]. As a consequence of this, for a MOSFET device, a gate voltage difference of at least 60 mV is needed to achieve an order of magnitude increase in drain current. This uncompressible SS stands as one of the major problems of modern ICs, due to the fact that circuits cannot have high performance and low standby power consumption at the same time.
To solve this issue, a novel transistor type called Tunnel FETs (TFET) has been proposed. TFETs rely on the peculiar quantum mechanical effect called band-to-band tunneling (BTBT). BTBT effect has been well-known for decades and has been successfully exploited in devices such as the Esaki (tunnel) diodes [3]. The main advantage of the TFET is the demonstrated ability to overcome the 60 mV/dec limitation [4] since it overcomes the n factor limitation stated above for thermionic devices like MOSFET.
However, the efforts to create a TFET structure that is able to compete against the state of the art CMOS technology have met several obstacles. The most pronounced of these problems is the extremely low current levels at ON state, which stems from the fact that device geometry is sub-optimal in maximizing the tunneling rate [5]-[7]. This issue of low ON current necessitates more optimized structures which can offer both the steep transition slope as well as high ON currents.
In order to overcome this difficulty, a novel device architecture called the Electron Hole Bilayer Tunnel FET (EHBTFET) was proposed and studied by the inventors themselves and other scientists in several publications [8]-[12]. The device utilizes the tunneling between electrostatically-induced two-dimensional electron and hole gases (2DEG and 2DHG, respectively). The device architecture consists of a thin semiconductor layer sandwiched between two asymmetrically-placed gate stacks as seen in FIG. 1. The energy band structure is such that BTBT occurs only when the energy levels of the electron and hole gases align. Since the channel is very thin, the tunneling distance from one carrier layer to the other is very small and hence the tunneling rate is much higher compared to the conventional TFETs. This enables the EHBTFET to have a step-like (<<60 mV/dec) turn-on characteristic [12].
Even though the EHBTFET device characteristics are extremely promising, there are several issues with its original implementation which undermine its feasibility. First, the process flow for the integration of such thin semiconductors with asymmetrically placed gates is highly non-trivial. The second issue is scaling; the underlap regions which are required to suppress the leakage current from the source and drain cannot be shrunk below a certain value, which adds additional undesired area in the device layout. Finally, the underlap regions add an extra amount of capacitance which slows the device switching.